Analysis of Power Efficient Modulo 2n+1 Adder Architectures

@inproceedings{Nikolos2016AnalysisOP,
  title={Analysis of Power Efficient Modulo 2n+1 Adder Architectures},
  author={D. G. Nikolos and H. T. Vergos and Costas Efstathiou},
  year={2016}
}
Two modified architectures for modulo 2n+1 adders are introduced in this paper. Only some of the carries of modulo 2n+1 addition are computed in sparse carry computation unit present in first architecture. This sparse approach is introduced by inverted circular idempotency property of the parallel-prefix carry operator and in this modified pre-processing… CONTINUE READING