Analysis of One Step Majority Logic Decoders Constructed From Faulty Gates

@article{Chilappagari2006AnalysisOO,
  title={Analysis of One Step Majority Logic Decoders Constructed From Faulty Gates},
  author={S. Chilappagari and Milos Ivkovic and Bane Vas{\'i}c},
  journal={2006 IEEE International Symposium on Information Theory},
  year={2006},
  pages={469-473}
}
In this paper we propose an analytical method to evaluate the performance of one step majority logic decoders constructed from faulty gates. We analyze the decoder under the assumption that the gates fail independently. We calculate the average bit error probability of such a decoder and apply the method to the special case of projective geometry codes. The method, however, applies to any regular low-density parity-check code of girth at least six but the calculations are much simpler for the… CONTINUE READING
Highly Cited
This paper has 46 citations. REVIEW CITATIONS

From This Paper

Figures, tables, and topics from this paper.

Citations

Publications citing this paper.
Showing 1-10 of 28 extracted citations

Analysis of Taylor-Kuznetsov memory using one-step majority logic decoder

2015 Information Theory and Applications Workshop (ITA) • 2015
View 6 Excerpts
Highly Influenced

Analysis of one-step majority logic decoding under correlated data-dependent gate failures

2014 IEEE International Symposium on Information Theory • 2014
View 3 Excerpts
Highly Influenced

Computing Linear Transformations With Unreliable Components

IEEE Transactions on Information Theory • 2017
View 1 Excerpt

Stochastic resonance in iterative decoding: Message passing and gradient descent bit flipping

2017 13th International Conference on Advanced Technologies, Systems and Services in Telecommunications (TELSIKS) • 2017

Coding theory for robust computing: Models, tools, and applications

2016 9th International Symposium on Turbo Codes and Iterative Information Processing (ISTC) • 2016
View 1 Excerpt

Reliability analysis of memory centric LDPC decoders under probabilistic storage failures

2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) • 2016
View 1 Excerpt

References

Publications referenced by this paper.
Showing 1-10 of 10 references

Expander codes

IEEE Trans. Information Theory • 1996
View 1 Excerpt

Information Storage in a Memory Assembled from Unreliable Components Coding Approaches to Fault Tolerance in Linear Dynamic Systems

A. Kuznetsov
IEEE Conference on Foundations of Computer Science • 1996

Information Storage in a Memory Assembled from Unreliable Components

A. Kuznetsov
Problems of Information Transmission vol. 9, pp. 254-264, Jul. 1973. • 1973
View 2 Excerpts

Reliable Information Storage in Memories Designed from Unreliable Components

M. Taylor
Bell System Technical Journal vol. 47, pp 2299-2337, Dec. 1968. • 1968
View 2 Excerpts

Similar Papers

Loading similar papers…