Analysis and minimization of substrate spurs in fractional-N frequency synthesizers

@article{Osmany2013AnalysisAM,
  title={Analysis and minimization of substrate spurs in fractional-N frequency synthesizers},
  author={S. Osmany and F. Herzel and J. C. Scheytt},
  journal={Analog Integrated Circuits and Signal Processing},
  year={2013},
  volume={74},
  pages={545-556}
}
This paper analyses substrate-related spurious tones in fractional-N phase-locked loops with integrated VCOs. Spur positions are calculated and experimentally verified as a function of the divider ratios of prescaler and programmable divider. For an integrated wideband PLL in SiGe BiCMOS technology the spur power levels are measured and compared with theoretical expectations. The power in these spurs is minimized by layout techniques shielding the reference input buffer. Spur minimization by… Expand
11 Citations
Design and layout strategies for integrated frequency synthesizers with high spectral purity
  • 4
  • PDF
An integrated frequency synthesizer in 130 nm SiGe BiCMOS technology for 28/38 GHz 5G wireless networks
  • 5
A comparison of two frequency synthesizer architectures in SiGe BiCMOS for FMCW radar
Charge pump design in 130 nm SiGe BiCMOS technology for low-noise fractional-N PLLs
  • 1
  • PDF
Suppression of Spur Chirps for Fractional-N PLL-Based Heterodyne FMCW SAR
Design of a low-jitter wideband frequency synthesizer for 802.11ad wireless OFDM systems using a frequency sixtupler
  • 4
8 Bit Segmented Current Steering DAC
  • PDF
...
1
2
...

References

SHOWING 1-10 OF 34 REFERENCES
A fractional-N synthesizer for software-defined radio with reduced level of spurious tones
  • 3
Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL
  • 113
  • PDF
An Integrated 18 GHz fractional-N PLL in SiGe BiCMOS technology for satellite communications
  • 18
A multiple modulator fractional divider
  • 207
  • PDF
A 4GHz Fractional-N synthesizer for IEEE 802.11a
  • 46
Modeling, design and characterization of a new low jitter analog dual tuning LC-VCO PLL architecture
  • 16
A New Mechanism Producing Discrete Spurious Components in Fractional- $N$ Frequency Synthesizers
  • 15
Spurious -Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL
  • K. Wang, A. Swaminathan, I. Galton
  • Engineering, Computer Science
  • 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers
  • 2008
  • 117
  • PDF
...
1
2
3
4
...