Analysis and characterization of PDN impedance and SSO noise of 4k-IO 3D SiP

@article{Takatani2012AnalysisAC,
  title={Analysis and characterization of PDN impedance and SSO noise of 4k-IO 3D SiP},
  author={Hiroki Takatani and Yosuke Tanaka and Hiroyuki Fujita and Yoshiaki Oizono and Yoshitaka Nabeshima and Toshio Sudo and Atsushi Fujitsu Limited Sakai and Shiro Uchiyama and Hiroyuki Ikeda},
  journal={2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)},
  year={2012},
  pages={185-188}
}
The this paper deals with the analysis of power distribution network (PDN) impedance and simultaneous switching output buffer (SSO) noise for a 3D system-in package (SiP) with 4k-IO widebus structure. The 3D SiP consisted of 3 stacked chips (a memory chip on the top, Si interposer in the middle, and a logic chip) and an organic package substrate. More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer and the logic chip. The PDN impedance for each chip was extracted… CONTINUE READING

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