Analysis and Design of a 10 Gbps Transimpedance Amplifier using 0.18μm CMOS technology


This paper examines the design of a 10 Gbps transimpedance amplifier (TIA) in 0.18 mum CMOS technology. In order to compensate for the high parasitic capacitances in the CMOS process, this design uses a shunt and series inductive peaking technique to achieve the required transimpedance bandwidth. A noise analysis on the input stage of the TIA is shown. This… (More)
DOI: 10.1109/CCECE.2006.277643


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