Analysis and Design of Nanoscale CMOS Storage Elements for Single-Event Hardening With Multiple-Node Upset

@article{Lin2012AnalysisAD,
  title={Analysis and Design of Nanoscale CMOS Storage Elements for Single-Event Hardening With Multiple-Node Upset},
  author={Sheng-Jie Lin and Yong-bin Kim and F. Lombardi},
  journal={IEEE Transactions on Device and Materials Reliability},
  year={2012},
  volume={12},
  pages={68-77}
}
The occurrence of a single event with a multiple-node upset is likely to increase significantly in nanoscale CMOS due to reduced device size and power supply voltage scaling. This paper presents a comprehensive treatment (model, analysis, and design) for hardening storage elements (memories and latches) against a soft error resulting in a multiple-node upset at 32-nm feature size in CMOS. A novel 13T memory cell configuration is proposed, analyzed, and simulated to show a better tolerance to… Expand
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