Analysis and Design of Finite Alphabet Iterative Decoders Robust to Faulty Hardware

@article{Dupraz2015AnalysisAD,
  title={Analysis and Design of Finite Alphabet Iterative Decoders Robust to Faulty Hardware},
  author={Elsa Dupraz and David Declercq and Bane V. Vasic and Valentin Savin},
  journal={IEEE Transactions on Communications},
  year={2015},
  volume={63},
  pages={2797-2809}
}
This paper addresses the problem of designing low-density parity check decoders robust to transient errors introduced by faulty hardware. We assume that the faulty hardware introduces errors during the message-passing updates, and we propose a general framework for the definition of the message update faulty functions. Within this framework, we define symmetry conditions for the faulty functions and derive two simple error models used in the analysis. With this analysis, we propose a new… CONTINUE READING
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