Analog circuit sizing using adaptive worst-case parameter sets

@article{Schwencker2002AnalogCS,
  title={Analog circuit sizing using adaptive worst-case parameter sets},
  author={Robert Schwencker and Frank Schenkel and Michael Pronath and Helmut E. Graeb},
  journal={Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition},
  year={2002},
  pages={581-585}
}
In this paper a method for nominal design of analog integrated circuits is presented that includes process variations and operating ranges by worst-case parameter sets. These sets are calculated adaptively during the sizing process based on sensitivity analyses. The method leads to robust designs with high parametric yield, while being much more efficient than design centering methods. 

Figures and Tables from this paper

Variability-aware automated sizing of analog circuits considering discrete design parameters

A new method is presented, based on SQP, Branch-and-Bound, and Realistic Worst-Case-Analysis, for analog design, which shows the efficiency and robustness of the results against variations in operating conditions and process parameters.

Direct search approach to integrated circuit sizing for high parametric yield

This study proposes a gradient-free approach to integrated circuit sizing that takes into account the statistical variations of device parameters and ranges of operating conditions and produces corners that are used in the optimisation loop of the circuit sizing process.

Discrete Sizing of Analog Integrated Circuits

This thesis presents two new approaches which use SQP and Branch-and-Bound to solve the sizing of the analog blocks of integrated circuits.

Tolerance Design of Analog Circuits using a Branch-and-Bound Based Approach

A new Branch-and-Bound based approach which allows the automatic computation of a robust design using classical and realistic worst case analysis is presented and the results of the sizing of three circuits show that the new approach is highly efficient.

Previous Works on Automated Analog IC Sizing

In this chapter, those approaches are briefly surveyed, focusing on the optimization techniques that are used, and the most significant aspects observed were the setup and the execution time, as well as the accuracy in the evaluation of the solutions.

Process Variation-Aware Analog Circuit Sizing: Uncertain Optimization

Chapter 5 provides an overview of uncertain optimization, and the application area: variation-aware analog circuit sizing. Two common efficiency enhancement methods for uncertain optimization are

Enhancing Variation-aware Analog Circuits Sizing

The application of the yield optimization methodology on the examples of a two-stage amplifier and a cascode amplifier shows that the approach can achieve higher quality in analog synthesis and unrivaled coverage of the analog design space when compared to traditional optimization techniques.

Enhancing analog yield optimization for variation-aware circuits sizing

This paper presents a novel approach for improving automated analog yield optimization using a two step exploration strategy that locates higher quality design points in terms of yield rate within less run time and without affecting the accuracy.

A yield-enhanced global optimization methodology for analog circuit based on extreme value theory

A practical variationaware circuit global optimization framework named GOYE, which shows the advantages on performance, yield and runtime and is the first one that allows users to control the target yield such that under-design or over-design can be avoided.

References

SHOWING 1-10 OF 16 REFERENCES

Circuit analysis and optimization driven by worst-case distances

A new deterministic method for parametric circuit design that is based on worst-case distances that uses standard circuit simulators and at the same time considers deterministic design parameters of integrated circuits at reasonable computational costs is presented.

The sizing rules method for analog integrated circuit design

Results of industrial applications to circuit sizing, design centering, response surface modeling and analog placement show the significance of the sizing rules method.

The Generalized Boundary Curve A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits

In this paper, a new method for analog circuit sizing with respect to manufacturing and operating tolerances is presented. Two types of robustness objectives are presented, i.e. parameter distances

Limit parameters: the general solution of the worst-case problem for the linearized case (IC design)

  • G. Muller
  • Mathematics
    IEEE International Symposium on Circuits and Systems
  • 1990
The use of limit parameters to determine the manufacturability of an IC design is addressed. On the basis of a sensitivity analysis of the circuit, a realistic worst-case (e.g. 3 sigma ) is

Worst-case analysis and optimization of VLSI circuit performances

A new approach for realistic worst-case analysis of VLSI circuit performances and a novel methodology for circuit performance optimization that is formulated as a constrained multicriteria optimization are presented.

Computer-aided design of analog and mixed-signal integrated circuits

This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs) and outlines progress on the various design problems involved.

Optimal design of a CMOS op-amp via geometric programming

A new method for determining component values and transistor dimensions for CMOS operational amplifiers (op-amps) is described, showing in detail how the method can be used to size robust designs, i.e., designs guaranteed to meet the specifications for a variety of process conditions and parameters.

Efficient analog circuit synthesis with simultaneous yield and robustness optimization

  • G. DebyserG. Gielen
  • Engineering
    1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)
  • 1998
The paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits and the strength of this methodology lies in the low CPU times needed to perform yield estimation.

OPTOMEGA: an environment for analog circuit optimization

  • M. KeramatR. Kielbasa
  • Computer Science
    ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)
  • 1998
The development of OPTOMEGA, an environment of analog circuit optimization, is presented which consists of the nominal circuit optimization by global optimization algorithms and the parametric yield or Average Quality Index (AQI) optimization.

Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition

The following topics are dealt with: semiconductor IP; formal verification; cooling; power management; defect oriented test; SAT and BDD techniques; low power design; mixed signal test; collaborative