Analog background calibration of a 10 b 40 Msample/s parallel pipelined ADC

Abstract

The sampling rate of an ADC often limits speed of a signal processing system. Sampling rate at the A/D interface can be increased by using multiple component ADCs that are time interleaved. Mismatches in offsets, gains, and sampling times among the component ADCs limit the performance of the ADC system. Previous time-interleaved ADC arrays use careful… (More)

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