Analog VLSI Implementation of Novel Hybrid Neural Network Multiplier Architecture
@inproceedings{Venkatesh2008AnalogVI, title={Analog VLSI Implementation of Novel Hybrid Neural Network Multiplier Architecture}, author={S. Venkatesh and P. Cyril and P. Raj}, year={2008} }
Neural networks are suitable to resolve problems where conventional resolution methods fail. The multipliers form a basic and important block in realising a neural network and this is commonly known as “Synapse”. Their roles are to multiply an input current with trained digital weights. Several research attempts to implement synapses. Some use numeric implementation whereas others use analogue circuit. Each of these implementations methods has its own advantages and drawbacks. Numeric… CONTINUE READING
Figures and Tables from this paper
One Citation
References
SHOWING 1-10 OF 14 REFERENCES
An MDAC synapse for analog neural networks
- Computer Science
- 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)
- 2004
- 12
- PDF
ANN digitally programmable analog synapse
- Engineering
- 42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356)
- 1999
- 4
VLSI neural network with digital weights and analog multipliers
- Computer Science
- ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)
- 2001
- 17
- PDF
Low voltage low power CMOS four-quadrant analog multiplier for neural network applications
- Engineering, Computer Science
- 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96
- 1996
- 22
A novel CMOS monolithic analog multiplier with wide input dynamic range
- Engineering, Computer Science
- Proceedings of the 8th International Conference on VLSI Design
- 1995
- 9
A 1.2 V CMOS four-quadrant analog multiplier
- Engineering
- Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97
- 1997
- 20
Design of current-mode digital-to-analog converter in hybrid architecture
- Engineering
- The 3rd International IEEE-NEWCAS Conference, 2005.
- 2005
- 4
- Highly Influential
A low-power CMOS analog multiplier
- Computer Science
- IEEE Transactions on Circuits and Systems II: Express Briefs
- 2006
- 63
- PDF
1.4 V supply, wide swing, high frequency CMOS analogue multiplier with high current efficiency
- Engineering, Computer Science
- 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)
- 2000
- 24