An ultra-low-power 902-928MHz RF receiver front-end in CMOS 90nm process


This paper presents a CMOS RF receiver frontend suitable for ultra-low-power operation. In order to achieve desired gain and linearity of receiver front-end at a 1V supply voltage, current reuse and optimum gate biasing techniques are employed. The proposed architecture includes merged LNA and mixer, operating in the sub-threshold region, and designed for… (More)
DOI: 10.1109/ISCAS.2012.6271726


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