An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop

@article{Bonetti2015AnOF,
  title={An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop},
  author={Andrea Bonetti and Adam Teman and Andreas Peter Burg},
  journal={2015 IEEE International Symposium on Circuits and Systems (ISCAS)},
  year={2015},
  pages={1850-1853}
}
Dual-edge-triggered (DET) synchronous operation is a very attractive option for low-power, high-performance designs. Compared to conventional single-edge synchronous systems, DET operation is capable of providing the same throughput at half the clock frequency. This can lead to significant power savings on the clock network that is often one of the major contributors to total system power. However, in order to implement DET operation, special registers need to be introduced that sample data on… CONTINUE READING