An optimized BIST test pattern generator for delay testing

@inproceedings{Girard1997AnOB,
  title={An optimized BIST test pattern generator for delay testing},
  author={Patrick Girard and Christian Landrault and V. Moreda and Serge Pravossoudovitch},
  booktitle={VTS},
  year={1997}
}
Highly Cited
This paper has 71 citations. REVIEW CITATIONS

From This Paper

Topics from this paper.

Citations

Publications citing this paper.
Showing 1-10 of 42 extracted citations

A new test pattern generator for high defect coverage in a BIST environment

ACM Great Lakes Symposium on VLSI • 2004
View 10 Excerpts
Highly Influenced

High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault Testability

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems • 2009
View 2 Excerpts
Highly Influenced

SIC pair generation in near-optimal time with carry-look ahead adders

2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) • 2018

A Multicycle Test Set Based on a Two-Cycle Test Set With Constant Primary Input Vectors

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems • 2015

An on-chip delay measurement using adjacency testable scan design

2015 7th International Conference on Information Technology and Electrical Engineering (ICITEE) • 2015
View 1 Excerpt

72 Citations

0510'98'03'09'15
Citations per Year
Semantic Scholar estimates that this publication has 72 citations based on the available data.

See our FAQ for additional information.

Similar Papers

Loading similar papers…