In this paper we propose a pipelined structure for systolic array-based matrix inversion. The main focus is to optimise the systolic structure for rapid prototyping of Kalman filters in FPGA devices. The design is implemented in VHDL language enabling potential users to effectively customise the structure for different size Kalman filters suitable for different applications. The proposed solution consists of pipeline registers, an innovative logic control unit, and a segmented Look Up Table based division scheme. The new architecture has an advantage of O(2n) resource consumption, compared to the O(n<sup>2</sup>) in other systolic array structures. The resulting precision error is within an acceptable range.