An open-loop clock generator for fast frequency scaling in 65nm CMOS technology

@article{Hoppner2011AnOC,
  title={An open-loop clock generator for fast frequency scaling in 65nm CMOS technology},
  author={Sebastian Hoppner and Stephan Henker and Holger Eisenreich and Rene Schuffny},
  journal={Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2011},
  year={2011},
  pages={264-269}
}
This paper presents an open-loop clock generator circuit for MPSoC applications. Based on an 8-phase reference clock a wide range of output frequencies with 50% duty cycle can be generated using a reverse phase switching technique. An optimized phase multiplexer enables operation at high input frequencies. Control signal synchronization allows the output frequency to be changed arbitrarily within a single clock cycle. The circuit has been implemented in 65nm CMOS technology. When operating at… CONTINUE READING

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SHOWING 1-10 OF 19 REFERENCES

and J

  • S. Wang, J. Zhu, Z. Qu
  • Wu, “Power efficient multimodulus programmable…
  • 2009
Highly Influential
3 Excerpts

A low - power , robust multimodulus frequency divider for automotive radio applications

  • R. Schuffny S. Hoppner, M. Nemes
  • Mixed Design of Integrated Circuits Systems
  • 2009

A low-power

  • S. Hoppner, R. Schuffny, M. Nemes
  • robust multimodulus frequency divider for…
  • 2009
1 Excerpt

An SEUtolerant programmable frequency divider

  • S. Yue, Y. Zhao, L. Fan
  • EuMC
  • 2008

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