An on-chip phase compensation technique in fractional-N frequency synthesis

@inproceedings{Rhee1999AnOP,
  title={An on-chip phase compensation technique in fractional-N frequency synthesis},
  author={W. Rhee and A. Ali},
  booktitle={ISCAS},
  year={1999}
}
Fractional-N frequency synthesis relaxes the phase-locked loop (PLL) design constraints to achieve a low noise performance while providing the same channel spacing. Inherent spurs generated by this system can be reduced with various techniques. The proposed architecture effectively compensates the periodic phase error in the time domain so that it is useful with widely used charge-pump PLLs. An on-chip tuning by a delay-locked loop (DLL) is also provided to make the system less dependent on the… CONTINUE READING
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