An on-chip clock generation scheme for faster-than-at-speed delay testing

@article{Pei2010AnOC,
  title={An on-chip clock generation scheme for faster-than-at-speed delay testing},
  author={Songwei Pei and Huawei Li and Xiaowei Li},
  journal={2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)},
  year={2010},
  pages={1353-1356}
}
Faster-than-at-speed testing provides an effective way for detecting and debugging small delay defects in modern fabricated chips. However, the use of external automatic test equipment for faster-than-at-speed delay testing could be costly. In this paper, we present an on-chip clock generation scheme which facilitates faster-than-at-speed delay testing for both launch on capture and launch on shift test frameworks. The required test clock frequency with a high resolution can be obtained by… CONTINUE READING

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Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers

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