An on-chip ADC BIST solution and the BIST enabled calibration scheme

@article{Jin2017AnOA,
  title={An on-chip ADC BIST solution and the BIST enabled calibration scheme},
  author={Xiankun Jin and Tao Chen and Mayank Jain and Arun Kumar Barman and David Kramer and Doug Garrity and Randall L. Geiger and Degang Chen},
  journal={2017 IEEE International Test Conference (ITC)},
  year={2017},
  pages={1-10}
}
This paper presents a complete on-chip ADC BIST solution based on a segmented stimulus error identification algorithm known as USER-SMILE. By adapting the algorithm for efficient hardware realization, the solution is implemented towards a 1Msps 12-bit SAR ADC on a 28nm CMOS automotive microcontroller. While sufficient test accuracy is demonstrated, the solution is further extended to correct linearity errors of ADC. The entire BIST and calibration circuitry occupies 0.028mm2 silicon area while… CONTINUE READING
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