An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs

@article{Singh2004AnOC,
  title={An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs},
  author={R. Singh and N. Bhat},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2004},
  volume={12},
  pages={652-657}
}
The input referred offset voltage occurring in the full latch V/sub DD/ biased sense amplifier has been analyzed extensively. The process variations in the matched nMOS and pMOS transistors have been accounted by /spl plusmn/2.5% variation in V/sub T/ and /spl plusmn/5% variation in /spl beta/, from typical values. Effect of various design parameters on the sense amplifier offset has been studied and reported. It has been shown that the rise time of the sense amplifier enable signal (SAEN) has… CONTINUE READING
Highly Cited
This paper has 50 citations. REVIEW CITATIONS

Citations

Publications citing this paper.
Showing 1-10 of 38 extracted citations

28-nm Latch-Type Sense Amplifier Modification for Coupling Suppression

IEEE Transactions on Very Large Scale Integration (VLSI) Systems • 2017
View 8 Excerpts
Highly Influenced

A robust design of SRAM sense amplifier for submicron technology

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology • 2010
View 9 Excerpts
Highly Influenced

A New Sense Amplifier Design with Improved Input Referred Offset Characteristics for Energy-Efficient SRAM

2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID) • 2017
View 5 Excerpts
Highly Influenced

Criterion to Evaluate Input-Offset Voltage of a Latch-Type Sense Amplifier

IEEE Transactions on Circuits and Systems I: Regular Papers • 2010
View 4 Excerpts
Highly Influenced

A New Sense Amplifier Topology with Improved Performance for High Speed SRAM Applications

2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) • 2016
View 2 Excerpts

51 Citations

0510'08'11'14'17
Citations per Year
Semantic Scholar estimates that this publication has 51 citations based on the available data.

See our FAQ for additional information.

References

Publications referenced by this paper.
Showing 1-10 of 12 references

The impact of intrinsic device fluctuations on CMOS SRAM cell stability

A. J. Bhavnagarwala, X. Tang, J. D. Meindl
IEEE J. Solid-State Circuits, vol. 36, pp. 658–665, Apr. 2001. • 2001

Threshold Voltage Mismatch Compensated Sense Amplifier for SRAM Memory Arrays

S. J. Lovett
U.S. Patent 6 181 621, Jan. 30, 2001. • 2001
View 1 Excerpt

A 1.4 ns access 700 MHz 288 kb SRAM macro with expandable architecture

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278) • 1999
View 1 Excerpt

The effect of statistical dopant fluctuations on MOS device performance

International Electron Devices Meeting. Technical Digest • 1996

A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers

K. Ishibashi, K. Takasugi, +9 authors T. Nishida
IEEE J. Solid-State Circuits, vol. 30, pp. 480–486, Apr. 1995. • 1995
View 1 Excerpt

Intra-die device parameter variation and their impact on digital CMOS gates at low-supply voltages

M. Eisele, J. Berthold, +3 authors W. Weber
IEDM Dig. Tech. Papers, 1995, pp. 67–70. • 1995

A 9-ns 16 Mb CMOS SRAM with offset compensated current sense amplifier

K. Seno, K. Knorpp, +9 authors K. Kobayashi
IEEE J. Solid-State Circuits, vol. 28, pp. 1119–1123, Nov. 1993. • 1993

Similar Papers

Loading similar papers…