An offset compensation technique for bandgap voltage reference in CMOS technology


A precision integrated bandgap voltage reference in 0.35μm CMOS technology is here presented. The circuit uses natural npn bipolar transistors as reference diodes. A particular attention was paid to the compensation of the several offsets that could strongly influence the performances of the reference. A very simple sample and hold technique for offset compensation is here presented. The proposed technique is straight forward for all bandgap topologies which use diodes with a terminal connected to the ground node or to the supply node. The temperature coefficient (TC) of the generated output voltage is 12.7ppm/°C versus about 245ppm/°C of the same circuit without offset compensation. A full description and an analytical expression for the proposed compensation technique are given. The results of the most relevant simulations are also reported. The circuit has been inserted in a test chip whose layout is shown.

DOI: 10.1109/ISCAS.2008.4541895

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@inproceedings{Ruzza2008AnOC, title={An offset compensation technique for bandgap voltage reference in CMOS technology}, author={Stefano Ruzza and Enrico Dallago and Giuseppe Venchi and Sergio Morini}, booktitle={ISCAS}, year={2008} }