An industrially effective environment for formal hardware verification

Abstract

The Forte formal verification environment for datapath-dominated hardware is described. Forte has proven to be effective in large-scale industrial trials and combines an efficient linear-time logic model-checking algorithm, namely the symbolic trajectory evaluation (STE), with lightweight theorem proving in higher-order logic. These are tightly integrated in a general-purpose functional programming language, which both allows the system to be easily customized and at the same time serves as a specification language. The design philosophy behind Forte is presented and the elements of the verification methodology that make it effective in practice are also described.

DOI: 10.1109/TCAD.2005.850814

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@article{Seger2005AnIE, title={An industrially effective environment for formal hardware verification}, author={Carl-Johan H. Seger and Robert B. Jones and John W. O'Leary and Thomas F. Melham and Mark Aagaard and Clark W. Barrett and Don Syme}, journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, year={2005}, volume={24}, pages={1381-1405} }