Voltage Controlled Delay Line with PFD for Delay Locked Loop in CMOS 90nm Technology
- IKiran I. Patel, IIPriyesh P. Gandhi, IIINilesh D. Patel, IVJaimini Prajapati
This paper presents a new voltage controlled delay line (VCDL) for a 30-phase 500MHz DLL. The new VCDL circuit solves the problem of flicker noise caused by the tail current source. The post-simulation result indicates that the VCDL has moderate linearity range, low Processing-Voltage-Temperature (PVT) sensitivity and good noise resistance. It can be perfectly applied in the 5Gbps Over-sampling based Clock and Data Recovery (CDR) circuit.