An improved voltage-controlled delay line for delay locked loops

Abstract

This paper presents a new voltage controlled delay line (VCDL) for a 30-phase 500MHz DLL. The new VCDL circuit solves the problem of flicker noise caused by the tail current source. The post-simulation result indicates that the VCDL has moderate linearity range, low Processing-Voltage-Temperature (PVT) sensitivity and good noise resistance. It can be perfectly applied in the 5Gbps Over-sampling based Clock and Data Recovery (CDR) circuit.

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Cite this paper

@article{Luo2011AnIV, title={An improved voltage-controlled delay line for delay locked loops}, author={Gang Luo and Xianjun Zeng}, journal={2011 3rd International Conference on Computer Research and Development}, year={2011}, volume={2}, pages={237-240} }