An improved method for RTL synthesis with testability tradeoffs

  title={An improved method for RTL synthesis with testability tradeoffs},
  author={Haidar Harmanani and Christos A. Papachristou},
A method for high-level synthesis with testability is presented withthe o~jective to generate self-testable RTL datapath structures. We base our approach on a new improved testability model that genemtes various testable design styJes while reducing the circuit sequential depth from controllable to observable registers. We follow the allocation method with an automatic test point selection algorithm and with an interactive tradeofl scheme which trades design area and delay with test quality… CONTINUE READING


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Publications referenced by this paper.
Showing 1-6 of 6 references

A Knowledge-Based System for Designing Testable VLSI Chips

IEEE Design & Test of Computers • 1985
View 4 Excerpts
Highly Influenced

Harmanani, \A Data Path Synthesis Method for Self-Testable Designs,

C. Papachristou, H. S. Chiu
View 3 Excerpts
Highly Influenced

Force-directed scheduling for the behavioral synthesis of ASICs

IEEE Trans. on CAD of Integrated Circuits and Systems • 1989
View 6 Excerpts
Highly Influenced

Automated Synthesis of Data Paths in Digital Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems • 1986
View 5 Excerpts
Highly Influenced

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