An improved low transition test pattern generator for low power applications

@article{Vellingiri2017AnIL,
  title={An improved low transition test pattern generator for low power applications},
  author={Govindaraj Vellingiri and Ramesh Jayabalan},
  journal={Design Automation for Embedded Systems},
  year={2017},
  volume={21},
  pages={247-263}
}
VLSI circuits are perceived to dissipate extra power during testing when compared with that of the normal function. Drastic heat may reduce circuit consistency, shoot up package cost, and even cause permanent damage to the circuit under test. Thus minimization of test power has gained increased significance. This paper explores the avenues in power minimization during test application in CMOS VLSI circuits since power consumption during testing is high when compared to normal operation. Design… CONTINUE READING