An experimental 0.6-V 57.5-fJ/conversion-step 250-kS/s 8-bit rail-to-rail successive approximation ADC in 0.18µm CMOS

@article{Fayomi2009AnE0,
  title={An experimental 0.6-V 57.5-fJ/conversion-step 250-kS/s 8-bit rail-to-rail successive approximation ADC in 0.18µm CMOS},
  author={Christian Jes{\'u}s B. Fayomi and Gilson I. Wirth and David M. Binkley and Akira Matsuzawa},
  journal={2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)},
  year={2009},
  pages={195-198}
}
An experimental 0.6-V 57.5-fJ/conversion-step 250-kS/s 8-bit rail-to-rail successive approximation (SA) analog-to-digital converter (ADC) implemented in a standard CMOS 0.18 µm digital process is presented. To overcome the input sampling switches limitation imposed by the low supply voltage we make use of a track-and-hold circuit based on a low-voltage, low-stress and reliable clock signal with a novel rail-to-rail track-and-latch comparator circuit. Power and area saving are achieved using… CONTINUE READING