An energy-efficient and scalable eDRAM-based register file architecture for GPGPU

@inproceedings{Jing2013AnEA,
  title={An energy-efficient and scalable eDRAM-based register file architecture for GPGPU},
  author={Naifeng Jing and Yao Shen and Yao Lu and Shrikanth Ganapathy and Zhigang Mao and Minyi Guo and Ramon Canal and Xiaoyao Liang},
  booktitle={ISCA},
  year={2013}
}
The heavily-threaded data processing demands of streaming multiprocessors (SM) in a GPGPU require a large register file (RF). The fast increasing size of the RF makes the area cost and power consumption unaffordable for traditional SRAM designs in the future technologies. In this paper, we propose to use embedded-DRAM (eDRAM) as an alternative in future GPGPUs. Compared with SRAM, eDRAM provides higher density and lower leakage power. However, the limited data retention time in eDRAM poses new… CONTINUE READING
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