An energy efficient 32nm 20 MB L3 cache for Intel® Xeon® processor E5 family

@article{Huang2012AnEE,
  title={An energy efficient 32nm 20 MB L3 cache for Intel® Xeon® processor E5 family},
  author={Min Huang and Moty Mehalel and Ramesh Arvapalli and Songnian He},
  journal={Proceedings of the IEEE 2012 Custom Integrated Circuits Conference},
  year={2012},
  pages={1-4}
}
A 20-way set associative 20MB energy efficient L3 this paper. The design uses 0.2119um2 cell and is manufactured in the 32nm second generation of high-K dielectric metal gate process with 9-copper layers. The power efficiency was achieved by employing advanced power saving schemes and effective Vccmin design techniques. The proposed L3 cache topology seamlessly supports a high density modular and energy efficient designs.