An energy efficient 18Gbps LDPC decoding processor for 802.11ad in 28nm CMOS

@article{Li2015AnEE,
  title={An energy efficient 18Gbps LDPC decoding processor for 802.11ad in 28nm CMOS},
  author={Meng Li and Jan-Willem Weijers and Veerle Derudder and Ilse Vos and Maxim Rykunov and Steven Dupont and Peter Debacker and Andy Dewilde and Yanxiang Huang and Liesbet Van der Perre and Wim Van Thillo},
  journal={2015 IEEE Asian Solid-State Circuits Conference (A-SSCC)},
  year={2015},
  pages={1-5}
}
The design of multi-Gbps LDPC decoder has become a hot topic in recent years as the demand of transformation towards 5G. An energy efficient 18Gbps LDPC decoder based on LDPC ASIP with half layer paralleled architecture is proposed. The feasibility of the design is proven by its demonstrator silicon in 28nm CMOS technology, with a record energy efficiency of 18.4 pJ/decoded bit and area efficiency of 23.8 Gbps/mm2 for the ½ coding rate working at 18.4Gbps. With frequency, voltage scaling and… CONTINUE READING

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