An encoder for a 5GS/s 4-bit flash ADC in 0.18/spl mu/m CMOS

@article{Sheikhaei2005AnEF,
  title={An encoder for a 5GS/s 4-bit flash ADC in 0.18/spl mu/m CMOS},
  author={Samad Sheikhaei and Shahriar Mirabbasi and Andr{\'e} Ivanov},
  journal={Canadian Conference on Electrical and Computer Engineering, 2005.},
  year={2005},
  pages={698-701}
}
In this paper, a high-speed encoder intended for a 5GS/S 4-bit flash analog-to-digital converter (ADC) is presented. To meet the speed and power targets of the ADC, low-swing signaling is used in all the internal sub-blocks of the ADC including the encoder. To further enhance the speed performance of the encoder, 2-stage pipelining is utilized. In addition, the encoder is implemented in current mode logic (CML). The circuit is designed and simulated in a 0.18 mum CMOS technology. It consumes 4… CONTINUE READING
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