An efficient virtual system clock for the wireless raspberry pi computer platform

  title={An efficient virtual system clock for the wireless raspberry pi computer platform},
  author={Diego Leonel Cadette Dutra and Edilson C. Corr{\^e}a and Claudio Luis de Amorim},
  journal={Concurrency and Computation: Practice and Experience},
Summary The use of Dynamic Voltage and Frequency Scaling (DVFS) by Energy-Efficient (EE) computer systems considerably increases the requirements regarding the design of efficient system clocks. [] Key Result Our experimental results validate the RVEC virtual system clock as an efficient system clock for the EE RasPi platform that runs the Linux operating system. Copyright © 2016 John Wiley & Sons, Ltd.
1 Citations

Computer architecture and high performance computing

This special issue of Concurrency and Computation Practice and Experience gathers eleven selected research articles that were previously presented at the Brazilian “XVII Simpósio em Sistemas



A Highly Effective System Clock for Energy-efficient Computer Systems

Energy-efficient computer systems are making increasing use of processors that have multiple core units, DVFS, and virtualization support. However, current system clocks have not been usually

Attaining Strictly Increasing and Precise Time Count in Energy-Efficient Computer Systems

  • D. DutraL. WhatelyC. Amorim
  • Computer Science
    2013 25th International Symposium on Computer Architecture and High Performance Computing
  • 2013
RVEC and HPGC can be effective alternatives to the system clock and the global clock respectively, in energy-efficient computer systems, especially for MPI applications running on beowulf clusters.

Counter availability and characteristics for feed-forward based synchronization

Modifications to the Linux and FreeBSD kernels are presented to enable any application to access all available counters in an unrestricted way, and then evaluated their stability, latency and robustness to stress.

High-Precision Relative Clock Synchronization Using Time Stamp Counters

This paper shows how to use a computer processor's time stamp counter register to provide a precise and stable time reference, via a high-precision relative clock synchronization protocol, which can achieve a synchronization precision in the order of 10 microseconds in a small-scale local area network using TSC registers.

Robust Synchronization of Absolute and Difference Clocks Over Networks

This work builds on the key observation that the measurement of time differences, and absolute time, requires separate clocks, both at a conceptual level and practically, with distinct algorithmic, robustness, and accuracy characteristics, and defines robust algorithms for the synchronization of the absolute and difference TSCclocks over a network.

Energy analysis of a DVFS based power strategy on ARM platforms

This paper analyzes Energy gains by implementing a DVFS based DSF power strategy on different ARM based processors (ARM1176JZF-S, CortexA9) and results showed significant amount of gains up to 52% for different execution conditions.

Clock synchronization in high‐end computing environments: a strategy for minimizing clock variance at runtime

A new software‐based clock synchronization scheme that provides high precision time agreement among distributed memory nodes and permits initial unbounded variations in time and corrects both slow and fast chimers (clock skew).

Energy-Efficient Design of Battery-Powered Embedded Systems

A modular approach for enhancing instruction level simulators with cycle-accurate simulation of energy dissipation in embedded systems and a profiler that relates energy consumption to the source code is presented.


A proposed control loop of DVFS technique has been introduced and SPICE simulation program results confirm the theory and suggest the technique can be considered as an effective mechanism for reducing processor power and energy.

Hardware Supported Synchronization Primitives for Clusters

This research developed a set of synchronization primitives for S-DSM on reconfigurable hardware, which implements an auxiliary synchronization network, which works in parallel to the data communication network.