An efficient statistical chip-level total power estimation method considering process variations with spatial correlation

@article{Hao2011AnES,
  title={An efficient statistical chip-level total power estimation method considering process variations with spatial correlation},
  author={Zhigang Hao and Sheldon X.-D. Tan and Guoyong Shi},
  journal={2011 12th International Symposium on Quality Electronic Design},
  year={2011},
  pages={1-6}
}
In this paper, we proposed an efficient statistical chip-level total power estimation method considering process variations with spatial correlation. Instead of computing dynamic power and leakage power separately, the new method compute the total power via circuit level simulation under realistic input testing vectors. To consider the process variations… CONTINUE READING