An efficient searching mechanism for dynamic NUCA in chip multiprocessors

Rapid growth in the cache sizes of Chip Multiprocessors (CMPs) to support high performance applications will lead to increase in wire-delays and unexpected access latencies. NUCA architectures help in managing the capacity and access time for such larger cache designs. Static NUCA (S-NUCA) has a fixed address mapping policy whereas dynamic NUCA (D-NUCA… CONTINUE READING