An efficient scheme for interprocessor communication using dual-ported RAMs

@article{Jagadish1989AnES,
  title={An efficient scheme for interprocessor communication using dual-ported RAMs},
  author={N. Jagadish and J. Mohan Kumar and Lalit M. Patnaik},
  journal={IEEE Micro},
  year={1989},
  volume={9},
  pages={10-19}
}
An approach for interprocessor interconnection is described in which communication between the processor nodes involves writing into and reading from a common memory area. The communicating processors do not have to contend for a common bus as in the case of shared-memory systems, since they have independent access to the common memory units shared between them. Only the memory access time of the processors limits the communication speed. Processor-to-processor communication does not use… CONTINUE READING
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