Corpus ID: 236772613

An efficient reverse-lookup table based strategy for solving the synonym and cache coherence problem in virtually indexed, virtually tagged caches

@article{Desai2021AnER,
  title={An efficient reverse-lookup table based strategy for solving the synonym and cache coherence problem in virtually indexed, virtually tagged caches},
  author={Madhav P. Desai and Aniket Anand Deshmukh},
  journal={ArXiv},
  year={2021},
  volume={abs/2108.00444}
}
Virtually indexed and virtually tagged (VIVT) caches are an attractive option for micro-processor level-1 caches, because of their fast response time and because they are cheaper to implement than more complex caches such as virtually-indexed physical-tagged (VIPT) caches. The level-1 VIVT cache becomes even simpler to construct if it is implemented as a direct-mapped cache (VIVT-DM cache). However, VIVT and VIVTDM caches have some drawbacks. When the number of sets in the cache is larger than… Expand

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References

SHOWING 1-7 OF 7 REFERENCES
Consistency management for virtually indexed caches
TLDR
Measurements show that a virtually indexed cache can be managed with nearly the same cost as that required to manage a physically indexed one, even when used by a virtual memory system that encourages and exploits sharing. Expand
U-cache: A cost-effective solution to the virtual cache synonym problem
TLDR
Performance evaluation based on memory reference traces from a real system shows that the U-cache, with only a few entries, performs almost as well as (in some cases outperforms) a fully-configured hardware-based solution when more than 95% of mappings are aligned. Expand
A new perspective for efficient virtual-cache coherence
TLDR
If a coherence protocol adheres to certain conditions, it operates effortlessly with virtual caches, without requiring reverse translations even in the presence of synonyms, in a new class of simple and efficient request-response protocols that use both self-invalidation and self-downgrade. Expand
A case for direct-mapped caches
  • M. Hill
  • Computer Science
  • Computer
  • 1988
Direct-mapped caches are defined, and it is shown that trends toward larger cache sizes and faster hit times favor their use. The arguments are restricted initially to single-level caches inExpand
Virtual-address caches. Part 1: problems and solutions in uniprocessors
TLDR
This survey introduces the problems and discusses solutions in the context of single-processor systems, to catalog all solutions, past and present, and to identify technology trends and attractive future approaches. Expand
A survey of cache coherence schemes for multiprocessors
Schemes for cache coherence that exhibit various degrees of hardware complexity, ranging from protocols that maintain coherence in hardware, to software policies that prevent the existence of copiesExpand
IEEE draft standard 1754