An efficient locally pipelined FFT processor

@article{Yang2006AnEL,
  title={An efficient locally pipelined FFT processor},
  author={Liang Yang and Kewei Zhang and Hongxia Liu and Jin Huang and Shitan Huang},
  journal={IEEE Transactions on Circuits and Systems II: Express Briefs},
  year={2006},
  volume={53},
  pages={585-589}
}
The fast Fourier transform (FFT) is a very important algorithm in digital signal processing. The locally pipelined (LPPL) architecture is an efficient structure for FFT processor designing in a real-time embedded system. Two basic building blocks, to the LPPL FFT processor, the butterfly in pipeline, and address generating, are discussed in this brief. Based on the "deep" feedback to butterfly-2, a novel approach for pipelined architecture, the radix-2 single-path deep delay feedback… CONTINUE READING
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