An efficient design of non-linear CA based PRPG for VLSI circuit testing

@article{Das2004AnED,
  title={An efficient design of non-linear CA based PRPG for VLSI circuit testing},
  author={Sukanta Das and Debdas Dey and Subhayan Sen and Biplab K. Sikdar and Parimal Pal Chaudhuri},
  journal={ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)},
  year={2004},
  pages={110-112}
}
This paper reports the efficient design of Pseudo-Random Pattern Generator (<i>PRPG</i>) with linear time complexity. The PRPG is developed around the regular structure of non-linear Cellular Automata (CA). The application of proposed <i>PRPG</i> is demonstrated in designing on-chip Test Pattern Generator (<i>TPG</i>) for VLSI circuits. The quality of the <i>TPG</i> is as good as that designed with the existing schemes, employing maximal length linear <i>CA</i> incurring <i>O</i>(n<sup>3</sup… CONTINUE READING