An efficient and flexible host-FPGA PCIe communication library


A high-performance interconnection between a host processor and FPGA accelerators is in much demand. Among various interconnection methods, a PCIe bus is an attractive choice for loosely coupled accelerators. Because there is no standard host-FPGA communication library, FPGA developers have to write significant amounts of PCIe related code at both the FPGA side and the host processor side. A high-performance host-FPGA PCIe communication library holds the key to broadening the use of FPGA accelerators. In this paper we target efficiency and flexibility as two important features in such a library. We discuss the challenges in providing these features, and present our solution to these challenges. We propose EPEE, an efficient and flexible host-FPGA PCIe communication library and describe its design. We implemented EPEE in various generations of Xilinx FPGAs with up to 26.24 Gbps half-duplex and 43.02 Gbps full-duplex aggregate throughput in the PCIe Gen2 X8 mode; these are at the best utilization levels that a host-FPGA PCIe library can achieve. The EPEE library has been integrated into four different FPGA applications with different data usage patterns in various institutes.

DOI: 10.1109/FPL.2014.6927459

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@article{Gong2014AnEA, title={An efficient and flexible host-FPGA PCIe communication library}, author={Jian Gong and Tao Wang and Jiahua Chen and Haoyang Wu and Fan Ye and Songwu Lu and Jason Cong}, journal={2014 24th International Conference on Field Programmable Logic and Applications (FPL)}, year={2014}, pages={1-6} }