An asynchronous synthesis toolset using Verilog

  title={An asynchronous synthesis toolset using Verilog},
  author={Frank P. Burns and Delong Shang and Albert Koelmans and Alexandre Yakovlev},
  journal={Proceedings Design, Automation and Test in Europe Conference and Exhibition},
  pages={724-725 Vol.1}
We present a new CAD tool set for generating asynchronous circuits from high-level Verilog level-sensitive specifications. Initially high-level Verilog descriptions are compiled and converted into a novel intermediate Petri-net format. The intermediate format is subsequently passed to optimization tools and mapping tools where it is directly mapped into asynchronous datapath and control circuits using David Cells (DCs). Finally logic optimization tools are applied to generate speed independent… CONTINUE READING

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