An asymmetric SRAM cell to lower gate leakage

Abstract

We introduce a new Static Random Access Memory (SRAM) cell that offers high stability and reduces gate leakage power in caches while maintaining low access latency. Our design exploits the strong bias towards zero at the bit level exhibited by the memory value stream of ordinary programs. Compared to conventional symmetric high-performance cell, our new… (More)
DOI: 10.1109/ISQED.2004.1283728

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