An area efficient asynchronous gated ring oscillator TDC with minimum GRO stages

@article{Hwang2010AnAE,
  title={An area efficient asynchronous gated ring oscillator TDC with minimum GRO stages},
  author={Kyu-Dong Hwang and Lee-Sup Kim},
  journal={Proceedings of 2010 IEEE International Symposium on Circuits and Systems},
  year={2010},
  pages={3973-3976}
}
An 8-bit, 3-stage asynchronous gated ring oscillator (GRO) time-to-digital converter (TDC) is presented. It employs asynchronous techniques to achieve minimum GRO stages. This lead to about 40% to 70% gate count reduction compared to synchronous GRO-TDC. Count-missing, glitch, and unnecessary addition are eliminated. The uncorrupted noise shaping characteristic is obtained. The chip is implemented in a 0.18um CMOS technology. It occupies small area (140μm×310μm) and consumes low power (4mW to… CONTINUE READING

Citations

Publications citing this paper.

References

Publications referenced by this paper.
SHOWING 1-6 OF 6 REFERENCES

An efficient high-resolution 11-bit noise-shaping multipath gated ring oscillator TDC

  • 2008 IEEE Symposium on VLSI Circuits
  • 2008
VIEW 4 EXCERPTS
HIGHLY INFLUENTIAL

Balsara “1.3V 20ps time-to-digital converters for fre- quency synthesis in 90-nm CMOS,

R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, P.T
  • IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53,
  • 2006
VIEW 1 EXCERPT

All-digital PLL and transmitter for mobile phones

  • IEEE Journal of Solid-State Circuits
  • 2005
VIEW 1 EXCERPT