An area efficient 64-bit square root carry-select adder for low power applications

@article{He2005AnAE,
  title={An area efficient 64-bit square root carry-select adder for low power applications},
  author={Yajuan He and Chip Hong Chang and Jiangmin Gu},
  journal={2005 IEEE International Symposium on Circuits and Systems},
  year={2005},
  pages={4082-4085 Vol. 4}
}
The carry-select method has deemed to be a good compromise between cost and performance in carry propagation adder design. However, the conventional carry-select adder (CSL) is still area-consuming due to the dual ripple-carry adder structure. The excessive area overhead makes CSL relatively unattractive but this has been circumvented by the use of an add-one circuit introduced recently. In this paper, an area efficient square root CSL scheme based on a new first zero detection logic is… CONTINUE READING
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