An area and power efficient pipeline FFT processor for 8×8 MIMO-OFDM systems

@article{Yoshizawa2011AnAA,
  title={An area and power efficient pipeline FFT processor for 8×8 MIMO-OFDM systems},
  author={Shingo Yoshizawa and Atsushi Orikasa and Yoshikazu Miyanaga},
  journal={2011 IEEE International Symposium of Circuits and Systems (ISCAS)},
  year={2011},
  pages={2705-2708}
}
In this paper, we propose an area and power efficient pipeline FFT processor for 8×8 MIMO-OFDM systems. The proposed FFT processor is based on mixed-radix multipath delay commutator (MRMDC) architecture in terms of low complexity and high memory utilization. A conventional MRMDC FFT processor increases hardware scale due to delay commutators which are used to change the order of the input sequences. The proposed FFT processor employs pre- and post-commutators which can reduce delay elements and… CONTINUE READING

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