An architecture-level approach for mitigating the impact of process variations on extensible processors

@article{Kamal2012AnAA,
  title={An architecture-level approach for mitigating the impact of process variations on extensible processors},
  author={Mehdi Kamal and Ali Afzali-Kusha and Saeed Safari and Massoud Pedram},
  journal={2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)},
  year={2012},
  pages={467-472}
}
In this paper, we present an architecture-level approach to mitigate the impact of process variations on extended instruction set architectures (ISAs). The proposed architecture adds one extra cycle to execute custom instructions (CIs) that violate the maximum allowed propagation delay due to the process variations. Using this method, the parametric yield of manufactured chips will greatly improve. The cost is an increase in the cycle latency of some of the CIs, and hence, a slight performance… CONTINUE READING

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