An architecture for exploiting coarse-grain parallelism on FPGAs

Abstract

We propose the use of a novel architecture, called the Multi-Level Computing Architecture (MLCA) to efficiently exploit coarse-grain parallelism on FPGAs. The central component of the MLCA is its Control Processor (CP), which is analogous to an out-of-order scheduling unit of a superscalar processor. The CP schedules coarse-grain units of computation, or… (More)

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