An analytical model relating FPGA architecture and place and route runtime

Abstract

This paper presents an analytical model that relates the architectural parameters of an FPGA to the place-and-route runtimes of the FPGA CAD tools. We consider both a simulated annealing based placement algorithm employing a bounding-box wirelength cost function, and a negotiationbased A<sup>*</sup> router. We also show an example application of the model… (More)
DOI: 10.1109/FPL.2009.5272519

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@article{Chin2009AnAM, title={An analytical model relating FPGA architecture and place and route runtime}, author={Scott Y. L. Chin and Steven J. E. Wilton}, journal={2009 International Conference on Field Programmable Logic and Applications}, year={2009}, pages={146-153} }