An analysis of power reduction techniques in scan testing

@inproceedings{Saxena2001AnAO,
  title={An analysis of power reduction techniques in scan testing},
  author={Jayashree Saxena and Kenneth M. Butler and Lee Whetsel},
  booktitle={ITC},
  year={2001}
}
Power consumption during scan testing is becoming a concern. Circuit switching activity during scan shifting is high and results in high average and instantaneous power consumption. This paper presents a scheme for reducing power and provides analysis results on an industrial design. 
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References

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Showing 1-9 of 9 references

Automatable Scan Partitioning for Low Power Using External Control”, TI Provisional patent application filed

  • J. Saxena, L. Whetsel
  • 2001

Two Techniques for Minimizing Power Dissipation in Scan Circuits during Test Application

  • S. Chakravarthy, V. P. Dabholkar
  • Proceedings of the Third Asian Test Symposium,
  • 1994

Koimihski, “Combinational Profiles of Sequential Benchmark Circuits

  • F. Brglez, K. D. Bryan
  • IEEE Int. Symp. on Circuits and Systems (ISCAS),
  • 1989

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