An algorithm for nano-pipelining of circuits and architectures for a nanotechnology

Abstract

In this paper, we describe an algorithm to post-process a register-transfer level (RTL) architecture to enable gate-level pipelining or nano-pipelining for the nanotechnology based on resonant tunneling diodes (RTDs). Nano-pipelining offers the opportunity to obtain massivethroughput and, therefore, has applications in data-intensive algorithms such as digital signal processing (DSP). Since RTDs are a self-latching nanotechnology, nano-pipelining is an implicit property that should be exploited for this technology. The novelty of this work lies in exploring and demonstrating the benefits of nano-pipelining and presenting an algorithm for architectural nano-pipelining.

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Cite this paper

@article{Gupta2004AnAF, title={An algorithm for nano-pipelining of circuits and architectures for a nanotechnology}, author={Pallav Gupta and Niraj K. Jha}, journal={Proceedings Design, Automation and Test in Europe Conference and Exhibition}, year={2004}, volume={2}, pages={974-979 Vol.2} }