An Upper Bound on Expected Clock Skew in Synchronous Systems

@article{Kugelmass1990AnUB,
  title={An Upper Bound on Expected Clock Skew in Synchronous Systems},
  author={Steven D. Kugelmass and Kenneth Steiglitz},
  journal={IEEE Trans. Computers},
  year={1990},
  volume={39},
  pages={1475-1477}
}
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References

Publications referenced by this paper.
SHOWING 1-6 OF 6 REFERENCES

Parallel bitlevel pipelined VLSI designs for high - speed signal processing

  • W. Ochsenreiter
  • Proc . IEEE
  • 1987

A probabilistic model for clock skew

  • CA. May M. S. Paterson, W. L. Ruzzo
  • Proc . Znt . Conf . Systolic Arrays

Synchronizing large VLSI processcr arrays

  • H. T. Kung
  • IEEE Trans . Comput .

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