Corpus ID: 17413058

An Ultra-Low Power Harmonic-Free Multiphase DLL Using a Frequency-Estimation Selector

@inproceedings{Chang2009AnUP,
  title={An Ultra-Low Power Harmonic-Free Multiphase DLL Using a Frequency-Estimation Selector},
  author={Yi-Ming Chang and Ming-Hung Chang and Wei Hwang},
  year={2009}
}
This paper presents an all-digital multiphase delay-locked loop (ADMDLL) for wide-locking range and micro-power applications. To enhance locking range and locking speed of the ADMDLL, we proposed the adaptive successive approximation register-controlled (ASAR) algorithm, which uses the frequency-estimation selector (FES) to avoid harmonic lock issue. In addition, the FES can reuse the delay line to reduce circuit area and power dissipation significantly. By using the stack effect, the proposed… Expand
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Figures and Tables from this paper

Design and Implementation of Fast Locking and Harmonic Free in Multiphase Digital DLL – Robust to Process Variations
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