An Optimum Design of FFT Multi-Digit Multiplier and Its VLSI Implementation

@inproceedings{Yazaki2005AnOD,
  title={An Optimum Design of FFT Multi-Digit Multiplier and Its VLSI Implementation},
  author={Syunji Yazaki and K{\^o}ki Abe},
  year={2005}
}
We designed a VLSI chip of FFT multiplier based on simple Cooly Tukey FFT using a floating-point representation with optimal data length based on an experimental error analysis. The VLSI implementation using HITACHI CMOS 0.18μm technology can perform multiplication of 2 to 2 digit hexadecimal numbers 19.7 to 34.3 times (25.7 times in average) faster than software FFT multiplier at an area cost of 9.05mm. The hardware FFT multiplier is 35.7 times faster than the software FFT multiplier for… CONTINUE READING
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